The basic integrated circuit output buffer includes an input for receiving data signals of high and low potential, an output for delivering data signals propagated through the output buffer, and intermediate circuit elements which may include amplifier stages and predrivers. A signal at the input propagates through the data path defined by the intermediate circuit elements to the output with a characteristic propagation delay. A relatively large current carrying capacity primary pulldown transistor element is coupled at the output for sinking discharge current from the output to ground. A relatively large current carrying capacity primary pullup transistor element is coupled at the output for sourcing charging current to the output from a power supply.
In both MOS and bipolar integrated circuit output buffers and devices, the pulldown transistor element initiates a relatively large sinking current from the output to external ground for discharging the output load capacitance during transition from high to low potential at the output. The surge or acceleration of charge develops a voltage across the output ground lead inductance proportional to L di/dt. This potential difference generated by switching outputs results in a positive ground rise in potential at the static low outputs. This output ground bounce may typically be in the order of 0.5 to 3.5 volts above the external ground 0 volts for high output drive circuits with output levels switching between V.sub.cc and ground. Deceleration of the initial surge of sinking current develops another voltage across the output ground lead inductance causing a ground voltage undershoot in the output lead of opposite polarity from the ground bounce. The absolute value of the negative ground undershoot spike may be as great as or greater than the positive ground bounce spike.
Similarly in both MOS and bipolar output circuits, the pullup transistor element initiates a relatively large sourcing current from a power supply to the output for charging the output load capacitance during transition from low to high potential at the output. The initial surge or acceleration of sourcing current charge develops a voltage across the output power supply lead inductance proportional to L di/dt resulting in a drop in the output voltage at the static high output. This drop in the output voltage is referred to as supply voltage droop or V.sub.cc drop. Power supply voltage droop may be as great as for example 0.5 to 3.5 volts below the external supply voltage in high output drive circuits with output levels switching between V.sub.cc and ground. Deceleration of the surge of sourcing current charge through the pullup transistor element develops another voltage across the output supply lead inductance causing an output supply voltage overshoot of potential in the output lead of opposite polarity from the V.sub.cc droop. The positive spike of the V.sub.cc overshoot above the external supply voltage may be as great as the absolute value of the negative spike of V.sub.cc droop in the output lead.
The disruptive effects of this noise on the output ground and supply leads include pulsing of noise on input and internal circuit ground and power supply lines; radio frequency radiation interference (RFI) and electromagnetic induction interference (EMI) noise which may interfere with a host system; local shifts in the reference voltages for high and low potential data signals causing false data signals; and crosstalk with other outputs on a common bus. For example, a low output on an octal buffer line driver common bus may experience a rise with ground bounce causing a false high signal. These problems associated with output ground and supply noise are of increased concern in recent integrated circuits switching higher currents at higher speeds.
The phrase "transistor element" is used herein to refer to integrated circuit transistors from different IC technologies including MOS transistors such as NMOS, PMOS and CMOS transistor elements, and bipolar transistors including, for example, NPN and PNP transistor elements in transistor-transistor logic (TTL) and emitter coupled logic (ECL) circuits. The transistor elements are generically characterized as having a primary current path with primary current path first and second terminal leads or electrodes, and a third control terminal lead or electrode for controlling the conducting state of the primary current path. In the case of an NMOS transistor element, for example, the primary current path first terminal lead is the drain lead, the second terminal lead is the source lead, and the third control terminal lead is the gate lead, etc. In the case of a bipolar NPN transistor element, the primary current path first terminal lead is the collector lead, the second terminal lead is the emitter lead, and the control terminal lead is the base lead, etc. In the case of PMOS and PNP transistor elements, the role of the first and second terminal leads are the inverse from that of the NMOS and NPN transistor elements respectively.
An earlier U.S. Pat. No. 4,961,010, filed May 19, 1989 by the present inventor, describes an improvement upon the basic output buffer. A relatively small current carrying capacity secondary pulldown transistor element is coupled with its current path first and second terminal leads in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown delay resistance element of selected value is operatively coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements.
The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer after the characteristic propagation delay and before the primary pulldown transistor element control terminal lead. The secondary pulldown transistor element therefore initiates a relatively small discharge current from the output before turn on of the relatively large discharge current of the primary pulldown transistor element. The separate pulldown delay resistance element value is selected for turning on the primary pulldown transistor element a specified time constant delay after the secondary pulldown transistor element during transition from high to low potential at the output.
A feature of the arrangement set forth in U.S. Pat. No. 4,961,010 is that the early turn on of a small current carrying capacity secondary pulldown transistor element initiates pulldown at the output and sinking of current from the output at only a small current sinking level. The initial sinking current level and the charge acceleration are constrained by the size and internal resistance of the small current carrying capacity transistor element. As a result the positive ground rise of potential proportional to L di/dt is also constrained to a lower level, typically less than one half that of a conventional output buffer. Subsequent ground undershoot is similarly less. It is noted that the small sinking current is initiated only after the full propagation delay of an input signal propagating through the data path of the intermediate circuit elements to the output of the buffer circuit.
The separate pulldown delay resistance element and the parasitic capacitance of the primary pulldown transistor element form an RC delay network which delays turn on of the primary or large current carrying capacity pulldown transistor element. This delay is determined by the selected resistance value of the pulldown delay resistance element and consequent time constant of the RC delay network. An advantage of this arrangement is that the small secondary sinking current continues to discharge the charge stored in the output load capacitance during the time constant delay. Upon turn on of the primary large current carrying capacity pulldown transistor element a second positive ground rise of potential occurs. However, the second ground bounce is now also limited by the reduction in charge in the output load capacitance already effected by the early small secondary sinking current. The reduced sinking current level and charge level also constrains and limits subsequent ground undershoot.
According to U.S. Pat. No. 4,961,010, the ratio of current carrying capacities of the primary and secondary pulldown transistor elements and the value of the pulldown delay resistance element are selected to achieve the following objective. The first positive ground rise in potential (first ground bounce) caused by early turn on of the secondary pulldown transistor element, and the second positive ground rise in potential (second ground bounce) caused by later turn on of the primary pulldown transistor element are arranged to be substantially equal by the selection of parameter values. The prior application provides a new method and new IC structure for minimizing the positive ground bounce spike by dividing or bifurcating the ground bounce spike into two components. The two component spikes are equalized by adjusting the values of mask programmable separate components at the output. As a result, the two phase, two step or bifurcated turn on component ground spikes may be limited to a noise level typically less than half that of conventional output buffers.
In the circuit of U.S. Pat. No. 355,509 the ratio of current carrying capacities of the primary to secondary pulldown transistor elements is at least approximately 4 to 1 with a discrete delay resistor having a value of for example 5K ohms to equalize and minimize the component first and second ground bounce spikes. Typically the ratio of current carrying capacities of the primary to secondary pulldown transistor elements is in the range of approximately 4/1 to 7/1. In the case of MOS transistor elements this is accomplished by setting the ratio of the channel widths at the primary to secondary pulldown transistor elements at approximately at least 4 to 1, and in the range of 4/1 to 7/1 etc.
In order to accelerate turn off of the primary pulldown transistor element during the reverse transition from low to high potential at the output, the circuit of U.S. Pat. No. 4,961,010 provides a pulldown delay bypass transistor element having its current path first and second terminal leads coupled between the control terminal lead of the primary pulldown transistor element and ground. A pulldown delay bypass control circuit operatively couples the control terminal lead of the bypass transistor element to the control terminal lead of the secondary pulldown transistor element. This permits bypassing the pulldown delay resistance element for rapid turn off of the primary pulldown transistor element during transition from low to high potential at the output. Typically the bypass control circuit incorporates an inverting element for applying the proper polarity signal to the control terminal lead of the bypass transistor element.
U.S. Pat. No. 4,961,010 describes similar measures for reducing noise on the supply rail side of the output buffer. A relatively small current carrying capacity secondary pullup transistor element is coupled with its primary current path first and second terminal leads in parallel with the current path first and second terminal leads of the primary pullup transistor element. A separate pullup delay resistor element of selected resistance value is coupled in series between the control terminal leads of the secondary and primary pullup transistor elements.
The secondary pullup transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer after the characteristic propagation delay, but before the primary pullup transistor element control terminal lead. The secondary pullup transistor element initiates a relatively small charging current from a power supply to the output before turn on of the relatively large charging current of the primary pullup transistor element during transition from low to high potential at the output. The discrete delay pullup resistor element resistance value is selected for turning on the primary pullup transistor element a specified time constant delay after the secondary pullup transistor element.
The ratio of the current carrying capacities of the primary and secondary pullup transistor elements and the value of the pullup delay resistance element are selected to achieve the similar objective of bifurcating both the power droop and subsequent overshoot. The first negative power droop in potential (first V.sub.cc droop) caused by turn on of the secondary pullup transistor element, and the second negative power droop in potential (second V.sub.cc droop) caused by later turn on of the primary pulldown transistor element are arranged to be substantially equal by the selection of parameter values. To this end the ratio of current carrying capacities of the primary to secondary pullup transistor elements at least approximately 4 to 1 and preferably in the range of 4/1 to 7/1, with a separate delay resistor element having a value of for example one thousand ohms (1K ohms). For rapid turn off of the pullup transistor element during the transition from high to low potential at the output, a pullup delay bypass transistor element and pullup delay bypass control circuit bypass the pullup delay resistor element.
In a typical output buffer line driver the characteristic propagation delay of a signal from the input to the output is, for example, 4 ns, operating into a standard load capacitance of, for example, 50 pf. Using the circuit of U.S. Pat. No. 4,961,010, the ground bounce or rising ground voltage may be constrained to one half the conventional value without substantial additional increase in switching speed propagation delay. Such circuits are referred to herein as bifurcated turn on (BTO) output buffer circuits.